The present invention relates, in general, to a soldering process and a technique for controlling that process. More particularly, the present invention relates to a process for reflowing solder on an article and a method of controlling the operating parameters of a solder reflow furnace for obtaining acceptable soldering of electronic components.
Solder bumps are frequently attached to conductive regions, or solder pads, of a device such as an integrated circuit or a circuit board to allow for surface mounting of the device. If the device is an electronic component, the electronic component may be a semiconductor wafer or package that requires solder ball attachment, such as ball grid arrays (BGA) and chip scale packages (CSP). Pre-formed solder bumps may be automatically positioned on pre-fluxed solder pads using a variety of well-known techniques, including robotic pick-and-placing and stencil methods. Solder bump placement typically is followed by a reflow operation, which secures the solder bumps to the solder pads.
Solder bumps may also be formed from a solder paste, which includes both a solder alloy and a flux, applied to solder pads prior to the reflow operation using commonly known techniques such as screen-printing. As the solder paste is brought through the reflow process, the solder alloy xe2x80x9cballs upxe2x80x9d and forms a solder bump. In the reflow process, the article containing the pre-formed solder bumps or solder paste is treated in a solder reflow furnace, which generally comprises a conveyor belt running through an oven and passing through several different heating zones. In the hottest zone, the article is treated for only a short period of time, allowing the solder to reach a temperature high enough to cause the solder to melt and reflow. A cool-down cycle completes the reflow process.
In an exemplary process, a rapid thermal, radiation-heated furnace is used to reflow solder bumps on silicon wafers. The solder bumps may be made from either lead (Pb)/tin (Sn) solders or Pb-free solders. In order to achieve uniform solder bump formation, an optimal solder reflow furnace operating profile (comprising a combination of furnace zone temperatures and belt speed operating parameters) must be predetermined for each wafer type. Due to the difference in wafer surface characteristics, the wafer temperature profile during reflow, including the maximum temperature achieved by the wafer during the solder reflow process (referred to as the peak temperature), cannot easily be controlled. This can result in poor solder bump formation and low reliability of the assembled package. A controllable wafer temperature profile results in a controllable solder reflow bump formation, which improves die and assembled package reliability. To select an appropriate furnace operating profile, a functional or test wafer has often been used to measure the wafer peak temperature, time above the solid-liquidus stage, and wafer ramp and cooling rates in the solder reflow furnace. By matching the required wafer reflow specifications, an optimal furnace operating profile could be determined.
Unfortunately, running functional or test wafers to determine furnace operating profiles for each wafer type can be expensive and time-consuming. Further, this calibration process has the possibility of damaging functional wafers.
In view of the above, a need exists in the field of the present technology for more quickly and efficiently determining suitable operating parameters for configuring a furnace operating profile such that the solder reflow process for electronic components or other articles is optimized.